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DATA SHEET
MOS INTEGRATED CIRCUIT
PD98404
ADVANCED ATM SONET FRAMER
DESCRIPTION
The PD98404 NEASCOT-P30TM is an LSI for ATM applications, which can be used in ATM adapter boards for connecting PCs or workstations to an ATM network and can also be used in ATM hubs and ATM switches. This LSI provides the TC sub-layer functions in the SONET/SDH-base physical layer within the ATM protocol defined by the ATM Forum's UNI3.1 recommendations. This product's main functions include transmission functions such as mapping of ATM cells sent from the ATM layer to the payload field in a 155 Mbps SONET STS-3c/SDH STM-1 frame and transmission to PMD (Physical Media Dependent) sub-layer in the physical layer. Its reception functions include separation of the overhead from the ATM cells in data streams received from PMD sub-layer and transmission of the ATM cells to the ATM layer. In addition, this LSI includes a clock recovery function that extracts a reception sync clock from bit streams in received data and a clock synthesis function that generates a clock for transmissions. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. PD98404 User's Manual: S11821E
FEATURES
* * * * On-chip clock recovery/clock synthesis functions Provides TC sub-layer function for the ATM protocol's physical layer Supported frame formats include 155 Mbps SONET STS-3c/SDH STM-1 Conforms to ATM Forum UTOPIA interface Level 2 V1.0 (af-phy-0039.000 June 1995) Supports three UTOPIA interfaces: * Single PHY octet-level handshaking * Single PHY cell-level handshaking * Multi PHY mode Selectable to drop/bypass unassigned cells On-chip internal loopback functions for PMD layer loopback and ATM layer loopback Supports two PMD interfaces: serial and parallel * 155.52 Mbps serial interface * 19.44 MHz parallel interface Provides registers for writing/reading overhead information SOH (section overhead) :J0 byte, Z0 (first and second) bytes, F1 byte LOH (line overhead) :K1 byte, K2 byte POH (path overhead) :F2 byte, C2 byte, H4 byte Provides pseudo error frame transmit function for various errors Supports JTAG boundary scan test function (IEEE 1149.1) CMOS technology +3.3 V single power supply
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
* * *
*
* * * *
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S11822EJ4V0DS00 (4th edition) Date Published May 2000 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1997, 1999
PD98404
* Provides abundant OAM (Operation and Maintenance) functions Receive side Transmit side * Transmission of various alarm data * Source-triggered automatic loopback transmission Line RDI, Path RDI Line REI, Path REI * Command-specified transmission Line AIS, Path AIS * Pseudo error generation frame transmit functions LOS generated frame OOF, LOF generated frame LOP generated frame OCD, LCD generated frame B1 error generated frame B2 error generated frame B3 error generated frame * * * Detection of alarm and fault signals LOS (Loss Of Signal) OOF (Out Of Frame) LOF (Loss Of Frame) LOP (Loss Of Pointer) OCD (Out of Cell Delineation) LOC (Loss Of Cell delineation) Line RDI, Path RDI Line AIS, Path AIS Detection and display of quality loss sources B1 error, B2 error, B3 error, Line REI, Path-REI On-chip error counters B1 byte error counter (16-bit) B2 byte error counter (20-bit) B3 byte error counter (16-bit) Line REI error counter (20-bit) Path REI error counter (16-bit) Rx Frequency justification processing counter (12-bit) HEC error drop cell counter (20-bit) FIFO overflow drop cell counter (20-bit) Idle cell counter (20-bit)
ORDERING INFORMATION
Part number Package 144-pin plastic QFP (fine pitch) (20 x 20 mm)
PD98404GJ-KEU
2
Data Sheet S11822EJ4V0DS00
PD98404
SYSTEM CONFIGURATION EXAMPLE
The following is an example of a system configuration using the PD98404.
ATM adapter card application
Control memory
SAR chip PD98401A NEASCOT-S15TM
PHY chip PD98404 NEASCOT-P30
Optical fiber transceiver /receiver
19.44 MHz Oscillator Bus bridge
Hub (terminal side) application
Microprocessor
Oscillator
PD98404 NEASCOT-P30
Optical fiber transceiver /receiver
UTOPIA Level2
Switch device PD98412 NEASCOT-X15TM
PD98404 NEASCOT-P30
Optical fiber transceiver /receiver
Data Sheet S11822EJ4V0DS00
3
4
Serial to parallel Frame synchronization (A1, A2) Pointer processor
Cell synchronization HEC verification HEC correction
BLOCK DIAGRAM
UTOPIA interface signal
Cell descrambler
Rx FIFO, 7 cells
PMD interface signal
ATM layer interface
Clock recovery & clock synthesizer & PMD layer interface
Descrambler
Parallel to serial
+
Scrambler
+
Cell scrambler
HEC generator
Tx FIFO, 7 cells
Data Sheet S11822EJ4V0DS00
BIP generator (transmit side)
Transmission overhead processor (A1, A2, K2, Z2, G1, H1, H2, H3)
Reception overhead processor (K2, Z2, G1, H1, H2, H3)
Transmission overhead registers (J0, Z0, C2, K2,etc.)
Management interface signal
Controller interface
BIP generator (receive side)
Transmission timing generator
OAM controller (performance register, etc.)
Reception overhead registers (J0, Z0, C2, K2, etc.)
Interrupt source register Mode register
PD98404
PD98404
PIN CONFIGURATION
Test interface PMD interface
TEST0 - TEST2
RDIT, RDIC RCIT, RCIC TDOT, TDOC TCOT, TCOC TFKT, TFKC Serial
RDO0 - RDO7 RCLK RSOC RENBL_B EMPTY_B/RCLAV RADD0-RADD4 TDI0 - TDI7 TCLK TSOC
8
AIN1 REFCLK 2 8 PSEL0, PSEL1 RPD0 - RPD7 RPC 8 TPD0 - TPD7 TPC TFC Parallel
5 8
ATM layer interface
TENBL_B FULL_B/TCLAV TADD0 - TADD4 UMPSEL 5
PMDALM 3 PHYALM0 - PHYALM2 RxFP TxFP TFSS RCL TCL
MSEL MADD0 - MADD6 MD0 - MD7 CS_B DS_B/RD_B R/W_B/WR_B ACK_B/RDY_B PHINT_B Management interface 7 8
JDO
JMS
JCK
JTAG boundary scan interface
Remark
Active low pins are indicated with the suffix "_B" in this document.
JDI
Power supply, GND
GND, GND-TPE, GND-RPE GND-SP, GND-CS, GND-CR
JRST_B
VDD, VDD-TPE, VDD-RPE VDD-SP, VDD-CS, VDD-CR
RESET_B
Data Sheet S11822EJ4V0DS00
5
PD98404
PIN CONFIGURATION (TOP VIEW)
144-pin plastic QFP (fine pitch) (20 x 20 mm)
VDD JCK JDO JDI JMS JRST_B TEST0 TEST1 TEST2 PHYALM0 PHYALM1 PHYALM2 TFSS TxFP TCL GND TPD0 TPD1 TPD2 TPD3 TPD4 TPD5 TPD6 TPD7 TPC TFC VDD REFCLK GND-CS GND-CS AIN1 VDD-CS VDD-CS GND-CS VDD-SP VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
GND GND RADD4 RADD3 RADD2 RADD1 RADD0 RDO7 RDO6 RDO5 RDO4 RDO3 RDO2 RDO1 RDO0 VDD RCLK RENBL_B RSOC EMPTY_B/RCLAV GND FULL_B/TCLAV TSOC TENBL_B TCLK VDD TDI7 TDI6 TDI5 TDI4 TDI3 TDI2 TDI1 TDI0 GND GND
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
VDD TADD4 TADD3 TADD2 TADD1 TADD0 GND RESET_B PHINT_B ACK/RDY_B R/W_B/WR_B DS_B/RD_B CS_B VDD MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 GND UMPSEL MADD6 MADD5 MADD4 MADD3 MADD2 MADD1 MADD0 MSEL PMDALM RCL RxFP VDD
6
GND GND-SP VDD-TPE TFKT TFKC GND-TPE TCOT TCOC VDD-TPE GND-TPE TDOT TDOC VDD-TPE GND-RPE RCIT RCIC VDD-RPE RDIT RDIC GND-RPE GND-CR VDD-CR RPC VDD RPD0 RPD1 RPD2 RPD3 RPD4 RPD5 RPD6 RPD7 PSEL0 PSEL1 GND GND
Data Sheet S11822EJ4V0DS00
PD98404
PIN ALLOCATION
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin name VDD JCK JDO JDI JMS JRST_B TEST0 TEST1 TEST2 PHYALM0 PHYALM1 PHYALM2 TFSS TxFP TCL GND TPD0 TPD1 TPD2 TPD3 TPD4 TPD5 TPD6 TPD7 TPC TFC VDD REFCLK GND-CS GND-CS AIN1 VDD-CS VDD-CS GND-CS VDD-SP VDD Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin name GND GND-SP VDD-TPE TFKT TFKC GND-TPE TCOT TCOC VDD-TPE GND-TPE TDOT TDOC VDD-TPE GND-RPE RCIT RCIC VDD-RPE RDIT RDIC GND-RPE GND-CR VDD-CR RPC VDD RPD0 RPD1 RPD2 RPD3 RPD4 RPD5 RPD6 RPD7 PSEL0 PSEL1 GND GND Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Pin name VDD RxFP RCL PMDALM MSEL MADD0 MADD1 MADD2 MADD3 MADD4 MADD5 MADD6 UMPSEL GND MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 VDD CS_B DS_B/RD_B R/W_B/WR_B ACK_B/RDY_B PHINT_B RESET_B GND TADD0 TADD1 TADD2 TADD3 TADD4 VDD Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Pin name GND GND TDI0 TDI1 TDI2 TDI3 TDI4 TDI5 TDI6 TDI7 VDD TCLK TENBL_B TSOC FULL_B/TCLAV GND EMPTY_B/RCLAV RSOC RENBL_B RCLK VDD RDO0 RDO1 RDO2 RDO3 RDO4 RDO5 RDO6 RDO7 RADD0 RADD1 RADD2 RADD3 RADD4 GND GND
Data Sheet S11822EJ4V0DS00
7
PD98404
PIN NAMES
ACK_B AIN1 CS DS_B EMPTY_B FULL_B GND GND-RPE GND-CR GND-CS GND-SP GND-TPE JCK JDI JDO JMS JRST_B
: Read/write Cycle Receive Acknowledge : External Filter Connection : Chip Select : Data Strobe : Output Buffer Empty : Buffer Full : Ground : Ground for Receive PECL Buffer : Ground for Clock Recovery Circuit : Ground for Clock Synthesis : Ground for Serial/Parallel Circuit : Ground for Transmit PECL Buffer : JTAG Clock : JTAG Data Input : JTAG Data Output : JTAG Mode Select : JTAG Reset
REFCLK RENBL_B RESET_B RPC RPD0-RPD7 RSOC RxFP R/W_B
: System Clock : Receive Data Enable : System Reset : Receive Parallel Data Clock : Receive Parallel Data : Receive Start Address of ATM Cell : Receive Frame Pulse : Read/write Control
TADD0-TADD4 : Transmit PHY Device Address TCL TCLAV TCLK TCOC TCOT TDI0-TDI7 TDOC TDOT TENBL_B TEST0-TEST2 TFC TFKC TFKT TFSS : Internal Transmit System Clock : Transmit Cell Available : Transmit Data Transferring Clock : Transmit Clock Output Complement : Transmit Clock Output True : Transmit Data Input from the ATM Layer : Transmit Data Output Complement : Transmit Data Output True : Transmit Data Enable : Test Mode Pin : Transmit Reference Clock : Transmit Reference Clock Complement : Transmit Reference Clock True : Transmit Frame Set Signal : Transmit Parallel Data Clock : Transmit Parallel Data : Transmit Start Address of ATM Cell : Transmit Frame Pulse : Utopia Multi-PHY Mode Select : Supply Voltage for Logic Circuit : Voltage Supply for Receive PECL Buffer : Voltage Supply for Clock Recovery Circuit : Voltage Supply for Clock Synthesis : Voltage Supply for Serial/Parallel Circuit : Voltage Supply for Transmit PECL Buffer : Write Select
MADD0-MADD6 : Management Interface Address Bus MD0-MD7 MSEL PHINT_B PHYALM0PHYALM2 PMDALM : PMD Device Alarm : Management Interface Data Bus : Management Interface Mode Select : Physical Interrupt : PHY Alarm Detection
TPC TPD0-TPD7 TSOC TxFP UMPSEL VDD VDD-RPE VDD-CR VDD-CS VDD-SP VDD-TPE WR_B
PSEL0, PSEL1 : PMD Mode Select RADD0-RADD4 : Receive PHY Device Address RCIC RCIT RCL RCLAV RCLK RD_B RDIC RDIT RDO0-RDO7 RDY_B : Receive Clock Input Complement : Receive Clock Input True : Internal Receive System Clock : Receive Cell Available : Receive Data Transferring Clock : Read Select : Receive Data Input Complement : Receive Data Input True : Receive Data Output : Ready Signal
8
Data Sheet S11822EJ4V0DS00
PD98404
1. PIN FUNCTIONS
1.1 PMD Interface
Pin name RDIT Pin No. 54 I/O level P-ECL True(+) RDIC 55 P-ECL Complement(-) RCIT 51 P-ECL True(+) RCIC 52 P-ECL Complement(-) TDOT 47 P-ECL True(+) TDOC 48 P-ECL Complement(-) TCOT 43 P-ECL True(+) O Serial transmit clock output (155.52 MHz). When PSEL [1:0] is set to 00, the clock generated by the internal synthesizer PLL is output as the transmit clock. When PSEL [1:0] is set to 01, the clock supplied to TFKT/TFKC is output. TCOC 44 P-ECL Complement(-) O Depending on the mode selected, the transmit data may be latched by the receive clock for output. Even in such a case, this pin outputs the clock of the internal synthesizer or the clock input to the TFKT/TFKC pin in accordance with the setting of the PSEL[1:0] pins. It does not output the receive recovery clock. TFKT 40 P-ECL True(+) TFKC 41 P-ECL Complement(-) RPD0RPD7 61-68 TTL* I Parallel receive data input. When PSEL [1:0] is set to 1X, these pins input receive data. The data is sampled in sync with the rising edge of parallel receive clock RPC. RPC 59 TTL* I Parallel receive clock input (19.44 MHz). When PSEL [1:0] is set to 1X to select parallel mode, this pin inputs a 19.44 MHz receive clock. TPD0TPD7 17-24 TTL* O Parallel transmit data output. When PSEL [1:0] is set to 1X to select parallel mode, these pins output transmit data in sync with the rising edge of PC. TPC 25 TTL* O Parallel transmit clock output. When PSEL [1:0] is set to 1X, this pin outputs the clock (19.44 MHz) supplied to TFC. I I Serial transmit clock input (155.52 MHz). When PSEL [1:0] is set to 01, the input is used as the transmit clock. O O Serial transmit data output. The data is output in sync with the rising edge of the serial clock TCOT. I I I I/O I Function Serial receive data input. When PSEL [1:0] is set to 00, the data is sampled on a clock recovered by the internal clock recovery PLL. When PSEL [1:0] is set to 01, the data is sampled on the clock input to RCIT/RCIC. Serial receive clock input (155.52 MHz). When PSEL [1:0] is set to 01, the input is used as a receive clock.
(1/2)
Data Sheet S11822EJ4V0DS00
9
PD98404
(2/3)
Pin name TFC Pin No. 26 I/O level TTL* I/O I Function Parallel transmit clock input. When PSEL [1:0] is set to 1X to select parallel mode, this pin inputs a parallel transmit clock of 19.44 MHz. If the TxCL bits [1:0] of the MDR1 register are set to 10 in the serial mode with PSEL[1:0] = "00", input the 19.44 MHz source clock of the internal clock synthesizer PLL. REFCLK 28 TTL* I Reference clock input. This pin supplies a system clock of 19.44 MHz to the internal clock recovery/synthesizer. Always input this clock. PSEL0, PSEL1 69, 70 TTL* I PMD interface mode select input. These pins select the interface mode of the PMD layer to be used. PSEL [1:0] = 00 :Serial mode. The clock generated by the internal clock recovery/synthesizer PLL is used for transmission and reception. PSEL [1:0] = 01 :Serial mode. The clock input of the external RCIT/RCIC and TFKT/TFKC is used for transmission and reception. PSEL [1:0] = 1x:Parallel mode. The clock input of RPC and TFC is used. AIN1 31 Analog O This pin connects the loop filter of the internal synthesizer PLL. Leave open. PMDALM 76 TTL* I PMD layer alarm signal input. The signal level of this pin is reflected in the state bit of an internal register. The transition of the bit can be used as an interrupt source. device is input. PHYALM0PHYALM2 10-12 TTL* O PHY layer alarm detection signal output. These pins output a signal indicating that an internally monitored error state (PMDALM, CMDARM, LOS, OOF, LOF, LOP, OCD, LCD, Line AIS, Path AIS, Line RDI, or Path RDI) has been detected. The pins can output an error either singly or in combination. The type of the error to be indicated is selected by setting the internal AMPR, AMR1, and AMR2 registers. For details on use, refer to 3.5 Alarm Report Pins The state signal from a peripheral
(PHYALM[2:0], (S11821E).
RxFP 74 TTL* O
PMDALM)
in
PD98404
User's
Manual
Frame pulse output for the receive side (8 kHz). This pin outputs a pulse signal at one-clock intervals in sync with the RCL clock in the frame synchronization state.
10
Data Sheet S11822EJ4V0DS00
PD98404
(3/3)
Pin name TxFP Pin No. 14 I/O level TTL* I/O O Function Frame pulse signal output for the transmit side (8 kHz). This pin outputs a pulse signal at one-clock intervals in sync with the TCL clock. TFSS 13 TTL* I Transmit frame output disable signal input. When the signal is high, the transmit frame output stops. When the signal is low, transmission starts from the beginning of a frame. The PD98404 samples this signal at the rising edge of the TCL clock. The transmit frame output is resumed at the ninth rising edge of the TCL clock after the rising edge at which the high level of this signal was last detected. RCL 75 TTL* O Internal system clock output for the receive side (19.44 MHz). This pin outputs the receive clock divided by 8. The source receive clock depends on the selected mode, which is either the clock generated by the internal clock recovery PLL or the clock supplied from the RCIT/RCIC and RFC pins. Clock output from this pin is stopped while the device is being reset. TCL 15 TTL* O Internal system clock output of the transmit side (19.44 MHz). This pin outputs the transmit clock divided by 8. The source transmit clock depends on the selected mode, which is either the clock generated by the internal synthesizer or the clock supplied from the TCIT/TCIC and TFC pins. Clock output from this pin is stopped while the device is being reset.
1.2 ATM layer interface
Pin name RDO0RDO7 Pin No. 130-137 I/O level TTL* I/O O state) Receive data output. Function
(1/2)
(2 or 3- These pins form an 8-bit data bus that outputs receive data to an ATM layer device. The data is output in sync with the rising edge of the RCLK clock. These pins operate in two or three states, depending on the UTOPIA interface mode.
RCLK
128
TTL*
I
Receive clock input. This pin supplies a clock of up to 40 MHz for receive data transfer.
RSOC
126
TTL*
O state)
Receive cell start position signal output. receive cell. This pin operates in two or three states, depending on the UTOPIA interface mode.
(2 or 3- This pin outputs a signal indicating the position of the first byte of a
RENBL_B
127
TTL*
I
Receive enable signal input. This pin inputs a signal indicating that the ATM layer is ready to receive data.
Data Sheet S11822EJ4V0DS00
11
PD98404
(2/2)
Pin name EMPTY_B/ RCLAV Pin No. 125 I/O level TTL* I/O O Function Receive FIFO data transfer disable signal output or
(2 or 3- receive FIFO cell data transfer enable signal output. state) This pin functions as either EMPTY_B (2-state operation) or RCLAV (3-state operation), depending on the selected mode of the UTOPIA interface. EMPTY_B indicates that the receive FIFO has no receive data bytes to be transferred to the ATM layer. RCLAV indicates that the receive FIFO has data of at least once cell to be transferred to the ATM layer. This pin operates in two or three states, depending on the UTOPIA interface mode.
RADD0RADD4 TDI0TDI7
138-142
TTL*
I
PHY address input for the receive side. In multi-PHY mode, these pins input the address of the PHY layer device to be selected.
111-118
TTL*
I
Transmit data input. These pins form an 8-bit data bus that inputs transmit data. The data is input in sync with the rising edge of the TCLK clock.
TCLK
120
TTL*
I
Transmit clock input. This pin inputs a clock of 20 to 40 MHz for transmit data transfer. Caution The PD98404 also uses this clock as the system clock of the management interface block. Therefore, always input a clock of 20 MHz or higher.
TSOC
122
TTL*
I
Transmit cell start position input. This pin inputs a signal indicating the position of the first byte of the transmit cell input to the PD98404.
TENBL_B
121
TTL*
I
Transmit enable input. This pin inputs a signal indicating that an ATM layer device is outputting valid transmit data to TDI0 - TDI7.
FULL_B/ TCLAV
123
TTL*
O
Transmit FIFO data transfer disable signal output or transmit FIFO
(2 or 3- cell data transfer enable signal output. state) This pin functions as either FULL_B (2-state operation) or TCLAV (3state operation), depending on the selected UTOPIA interface mode. FULL_B indicates that the transmit FIFO has no free area to receive transmit data. TCLAV indicates that the transmit FIFO has a free area of at least one cell for storing transmit data. This pin operates in two or three states, depending on the UTOPIA interface mode.
TADD0TADD4 UMPSEL
103-107
TTL*
I
PHY address input for the transmit side. When used in multi-PHY mode, these pins input an address for selecting a PHY layer device.
85
TTL*
I
Multi-PHY mode select signal input. * * When the signal is high, multi-PHY mode is selected. When the signal is low, single PHY mode is selected.
12
Data Sheet S11822EJ4V0DS00
PD98404
1.3 Management interface
Pin name MSEL Pin No. 77 I/O level TTL* I/O I Function Mode select signal input. The level of input to this pin determines the management interface mode. MSEL = 1: MSEL = 0: Pin functions RD_B, WR_B, and RDY_B are selected. Pin functions DS_B, R/W_B, and ACK_B are selected. MADD0MADD6 78-84 TTL* I Address input. These pins form an address bus to input the address of an internal register of the PD98404. MD0-MD7 87-94 TTL* I/O (3state) CS_B 96 TTL* I 8-bit data bus. These pins form a data bus to read or write data of an internal register of the PD98404. Chip select signal input. When the signal is low, access to an internal register is enabled. DS_B/ RD_B 97 TTL* I Data strobe signal input or read signal input. This pin functions as either DS_B or RD_B, depending on the mode selected by the MSEL pin. MSEL = 0: This pin functions as DS_B to input the data strobe signal. MSEL = 1: This pin functions as RD_B to select read access. R/W_B/ WR_B 98 TTL* I Read/write signal input or write signal input. This pin functions as either R/W_B or WR_B, depending on the mode selected by the MSEL pin. MSEL = 0: This pin functions as R/W_B that inputs the read/write control signal. High: Read cycle Low: Write cycle MSEL = 1: This pin functions as WR_B that selects write access. ACK_B/ RDY_B 99 TTL* O (3state) Data acknowledge signal output or ready signal output. selected by the MSEL pin. MSEL = 0 : The pin functions as ACK_B that outputs the data strobe signal. MSEL = 1 : The pin functions as RDY_B that selects read access. PHINT_B 100 TTL* O Interrupt signal output. This pin notifies the host that an internal interrupt source has been detected. The pin is active low. This pin
(1/2)
functions as either ACK_B or RDY_B, depending on the mode
Data Sheet S11822EJ4V0DS00
13
PD98404
(2/2)
Pin name RESET_B Pin No. 101 I/O level TTL* I/O I Function System reset signal input. The signal initializes the PD98404. The input signal should be kept low for 1 s or more. Especially, in case of the power on, above-mentioned pulse width must be kept after the supply voltage reaches equal to or more than 90% at least. When the RESET_B signal is input, the following clock must be input according to the PMD interface mode. Serial mode : TCLK/RCLK clock Parallel mode : TCLK/RCLK and TFC/RPC clocks
1.4 JTAG boundary scan
Pin name JDI Pin No. 4 I/O level TTL* I/O I Boundary scan data input. When not being used, this pin should be grounded. JDO 3 TTL* O (3state) JCK 2 TTL* I Boundary scan clock input. When not being used, this pin should be grounded. JMS 5 TTL* I Boundary scan mode select signal input. When not being used, this pin should be grounded. JRST_B 6 TTL* I Boundary scan reset signal input. When not being used, this pin should be grounded. Boundary scan data output. When not being used, this pin should be left open. Function
Remark
Processing of JTAG boundary scan pins not used (during normal operation) The reason that the JRST_B pin is grounded when it is not used (during normal operation) is to better prevent malfunctioning of the JTAG logic. The JTAG pin may be also processed in either of the following ways: * Reset the JTAG logic without using the JRST_B pin Reset the JTAG logic by using the JMS and JCK pins and keep it in the reset status (the JRST_B pin is pulled up). Fix the JMS pin to 1 (pull up) and input 5 clock cycles or more to the JCK pin. * Reset the JTAG logic by using the JRST_B pin Input a low pulse of the same width as RESET_B of the PD98404 to the JRST_B pin. If both the JMS and JRST_B pins are pulled up and kept high, the JTAG logic is not released from the reset status. Therefore, the normal operation is not affected. Fix the input level of the JDI and JCK pins by pulling them down or up.
14
Data Sheet S11822EJ4V0DS00
PD98404
1.5 Internal test pins
Pin name TEST0TEST2 Pin No. 7-9 I/O level TTL* I/O I Function These pins are used to test the PD98404. In normal operation, all these pins should be grounded. TEST [2:0] =000 : Normal operation TEST [2:0] =Other than 000 : Test mode
1.6 Power and ground
Pin name VDD Pin No. 1, 27, 36, 60, 73, 95, 108, 119, 129 GND 16, 37, 71, 72, 86, 102, 109, 110, 124, 143, 144 VDD-TPE 39, 45, 49 Power supply (+3.3 V 5%) and ground for output PECL I/O. Any noise in this power supply will affect the jitter characteristics. GND-TPE 42, 46 means of eliminating this noise, such as a filter, is needed. A I/O Function Power supply (+3.3 V 5%) and ground for the general logic block.
VDD-RPE
53
-
Power supply (+3.3 V 5%) and ground for input PECL I/O. noise in this power supply will affect the jitter characteristics. means of eliminating this noise, such as a filter, is needed.
Any A
GND-RPE
50, 56
-
VDD-SP
35
-
Power supply (+3.3 V 5%) and ground for the serial /parallel block. Any noise in this power supply will affect the jitter characteristics. A means of eliminating this noise, such as a filter, is needed.
GND-SP
38
-
VDD-CS
32, 33
-
Power supply (+3.3 V 5%) and ground for the clock synthesizer PLL block. Any noise in this power supply will affect the jitter characteristics. A means of eliminating this noise, such as a filter, is needed.
GND-CS
29, 30, 34
-
VDD-CR
58
-
Power supply (+3.3 V 5%) and ground for the clock recovery PLL block. Any noise in this power supply will affect the jitter characteristics. A means of eliminating this noise, such as a filter, is needed.
GND-CR
57
-
Data Sheet S11822EJ4V0DS00
15
PD98404
1.7 Recommended connection of unused pins
Pin Each input pin at level other than P-ECL Recommended Connection of Unused Pins Connect to ground (parallel input pin in serial mode) RPD0 through RPD7, RPC, TFC (Multi-PHY pins in single PHY mode) TADD0 to TADD4, RADD0 through RADD4 (others) TFSS (essential) Each input pin at P-ECL level Output pin Pull up True(+) pins (TFKT, RCIT, RDIT) to 3.3 V. Connect Complement(-) pins (TFKC, RCIC, RDIC) to ground. Leave open. (Parallel input pins in serial mode) TPD0 to TPD7 TPC (others) TxFP, RxFP, TCL, RCL Output pin at P-ECL level Leave open. TDOT, TDOC, TCOT, TCOC AIN1 Leave Open. Because noise on this pin affects the characteristics of the internal PLL, do not wire a clock line in the vicinity.
16
Data Sheet S11822EJ4V0DS00
PD98404
2. ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings " " mark indicates portion which have been revised from old edition.
Item Power supply voltage Input/output voltage
Symbol VDD VI1/VO1 VI2/VO2
Condition
Ratings -0.5 to +4.6
Unit V V V C C
Pin other than P-ECL, analog level P-ECL, analog level
-0.5 to +6.6 or VDD +3.0 -0.5 to +4.6 or VDD +0.5 -45 to +85 -65 to +150
Operating temperature Storage temperature
TA Tstg
Caution
If even one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the values at which the product can be used without physical damage. Be sure not to exceed or fall below these values when using the product.
Capacitance
Parameter Input capacitance Output capacitance Input/output capacitance
Symbol CI CO CIO
Condition Frequency: = 1 MHz Frequency: = 1 MHz Frequency: = 1 MHz
MIN.
TYP. 6 6 6
MAX. 10 10 10
Unit pF pF pF
Recommended Operating Conditions
Parameter Power supply voltage Operating temperature range Low-level input voltage
Symbol VDD TA VIL1 VIL2
Condition
MIN. VDD x 0.95 -40
TYP. 3.3
MAX. VDD x 1.05 +85 0.8 VDD - 1.50 5.25 VDD - 0.40 1900
Unit V C V V V V mV
Pin other than P-ECL level pin P-ECL level pin Pin other than P-ECL level pin P-ECL level pin
0 VDD - 2.82 2.2 VDD - 1.49 300
High-level input voltage
VIH1 VIH2
Differential input voltage
VIDIFF2
Remark
P-ECL level pins : RDIT, RDIC, RCIT, RDIC, TDOT, TDOC, TCOT, TCOC, TFKT, TFKC Analog pins : AIN1
Data Sheet S11822EJ4V0DS00
17
PD98404
DC Characteristics (VDD = 3.3 0.15 V, TA = -40 to +85C)
Parameter Off-state output current Input leakage current Symbol IOZ ILI1 Condition VI = VDD or GND VI = VDD or GND Pin other than P-ECL level pin ILI2 Low-level output voltage VOL1 P-ECL level pin IOL = +8mA, VDD = 3.3 V Pin other than P-ECL level pin VOL2 RL = 50 , VT = VDD - 2 V P-ECL level pin High-level output voltage VOH1 IOH = -8 mA, VDD = 3.3 V Pin other than P-ECL level pin VOH2 RL = 50 , VT = VDD - 2 V P-ECL level pin Power supply current IDD During normal operation 200 450 mA VDD - 1.14 VDD - 0.92 VDD - 0.69 V 2.4 V VDD - 2.175 VDD - 1.975 VDD - 1.755 V 10 0.4 MIN. TYP. MAX. 10 10 Unit
A A
A
V
AC Characteristics (VDD = 3.3 0.15 V, TA = -40 to +85C) AC Test Condition The propagation delay time is defined as shown below.
0.7VDD Input pin 0.3VDD 0.5VDD
Output pin
0.5VDD
tPD
AC Testing Load Circuit
Device Under Test
CL = 50pF
18
Data Sheet S11822EJ4V0DS00
PD98404
Management Interface a) Internal register read
Parameter Address setup time (to DS_B [RD_B]) CS_B setup time (to DS_B [RD_B]) R/W_B[WR_B] setup time (to DS_B [RD_B]) Address hold time (to DS_B [RD_B]) CS_B hold time (to DS_B [RD_B]) R/W_B [WR_B] hold time (to DS_B [RD_B]) DS_B [RD_B] ACK_B [RDY_B] output delay time DS_B [RD_B] data output delay time DS_B [RD_B] ACK_B [RDY_B] float delay time DS_B [RD_B] data float delay time ACK data output delay time DS_B[RD_B] pulse width
Note
Symbol tSADDS tSCSDS tSRWDS tHADDS tHCSDS tHRWDS tVAKDS tVDADS tIAKDSR tIDADS tDDAAK tWDS tDSINT
Condition
MIN. 10 5 5 4 0 4
TYP.
MAX.
Unit ns
9 x tCYTK
ns ns ns ns ns
Load capacity = 50 pF Load capacity = 50 pF Load capacity = 50 pF Load capacity = 50 pF Load capacity = 50 pF 50 4 x tCYTK 5 15
15 20 30 45 10
ns ns ns ns ns ns ns
DS_B[RD_B]DS_B[RD_B] recovery time
Note tWDS defines the time during which the PD98404 can recognize DS_B [RD_B] as a low level, and does not define the pulse width of DS_B [RD_B] with which data can be accurately read. The time required for the PD98404 to make ACK_B [RDY_B] low after DS_B [RD_B] has gone low differs depending on the register to be accessed. Make DS_B [RD_B] high after confirming that ACK_B [RDY_B]. The time required for the PD98404 to make ACK_B [RDY_B] low after DS_B [RD_B] has gone low is "4 x TCLK clock cycle (tCYTK)" at best. So that any register can be read without using ACK_B [RDY_B], widen the pulse width of DS_B [RD_B] to at least to "4 x TCLK clock cycle". Remark tCYTK is the cycle of the TCLK clock.
Data Sheet S11822EJ4V0DS00
19
PD98404
(i) When MSEL = "0" (Motorola compatible)
MADD0 - MADD6 tSADDS CS_B tSCSDS MD0 - MD7 tVDADS DS_B tWDS R/W_B tSRWDS ACK_B tVAKDS tIAKDSR tHRWDS Invalid tDDAAK Data tIDADS tHCSDS tHADDS
(ii) When MSEL = "1" (Intel compatible)
MADD0 - MADD6 tSADDS CS_B tSCSDS MD0 - MD7 tVDADS RD_B tWDS WR_B tSRWDS RDY_B tVAKDS tIAKDSR tHRWDS Invalid tDDAAK Data tIDADS tHCSDS tHADDS
20
Data Sheet S11822EJ4V0DS00
PD98404
b) Internal register write
Parameter Address setup time (to DS_B [WR_B]) CS_B setup time (to DS_B [WR_B]) R/W_B[RD_B] setup time (to DS_B [WR_B]) Data setup time (to DS_B [WR_B]) Address hold time (to DS_B [WR_B]) CS_B hold time (to DS_B [WR_B]) R/W_B [WR_B] hold time (to DS_B [WR_B]) Data hold time (to DS_B [WR_B]) DS_B [WR_B] ACK_B [RDY_B] output delay time DS_B [WR_B] ACK_B [RDY_B] float delay time DS_B [WR_B] pulse width
Note
Symbol tSADDS tSCSDS tSRWDS
Condition
MIN. 10 5 5
TYP.
MAX.
Unit ns
9 x tCYTK
ns ns
tSDADS tHADDS tHCSDS tHRWDS
15 4 0 4
ns ns ns ns
tHDADS tVAKDS Load capacity = 50 pF
4 15
ns ns
tIAKDSW
Load capacity = 50 pF
10
ns
tWDS tDSINT
50 4 x tCYTK
ns ns
DS_B[WR_B]DS_B[WR_B] recovery time
Note tWDS defines the time during which the PD98404 can recognize DS_B [WR_B] as a low level, and does not define the pulse width of DS_B [WR_B] with which data can be accurately read. The time required for the PD98404 to make ACK_B [RDY_B] low after DS_B [WR_B] has gone low differs depending on the register to be accessed. Make DS_B [WR_B] high after confirming that ACK_B [RDY_B] has gone low. The time required for the PD98404 to make ACK_B [RDY_B] low after DS_B [WR_B] has gone low is "4 x TCLK clock cycle (tCYTK)" at best. So that any register can be write without using ACK_B [RDY_B], widen the pulse width of DS_B [WR_B] to at least to "4 x TCLK clock cycle". Remark tCYTK is the cycle of the TCLK clock.
Data Sheet S11822EJ4V0DS00
21
PD98404
(i) When MSEL = "0" (Motorola compatible)
MADD0 - MADD6 tSADDS CS_B tSCSDS MD0 - MD7 tSDADS DS_B tWDS R/W_B tSRWDS ACK_B tVAKDS tIAKDSW tHRWDS tHCSDS Data tHDADS tHADDS
(ii) When MSEL = "1" (Intel compatible)
MADD0 - MADD6 tSADDS CS_B tSCSDS MD0 - MD7 tSDADS WR_B tWDS RD_B tSRWDS RDY_B tVAKDS tIAKDSW tHRWDS tHCSDS Data tHDADS tHADDS
22
Data Sheet S11822EJ4V0DS00
PD98404
c) Internal register read/write (NEASCOT-S15 connection mode, MSEL = "0") (i) Read timing
Parameter Address setup time (to CS_B) R/W_B setup time (to CS_B) Address hold time (to CS_B) R/W_B hold time (to CS_B) DS_B hold time (to CS_B) DS_B data output delay time DS_B data float delay time CS_B pulse width DS_B pulse width Symbol tSADCS tSRWCS tHADCSR tHRWCSR tHDSCS tVDADS tIDADS tWCS tWDS Load capacity = 50 pF Load capacity = 50 pF 15 15 x tCYTK 4 x tCYTK Condition MIN. 10 10 5xtCYTK+10 15xtCYTK+10 15xtCYTK+10 30 + tCYTK 45 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
Remark
tCYTK is the cycle of the TCLK clock.
tSADCS tHADCSR tWCS CS_B MD0 - MD7 tHDSCS DS_B tWDS R/W_B tSRWCS tHRWCSR Data tVDADS
MADD0 - MADD6
tIDADS
Data Sheet S11822EJ4V0DS00
23
PD98404
(ii) Write timing
Parameter Address setup time (to CS_B) R/W_B setup time (to CS_B) Data setup time (to CS_B) Address hold time (to CS_B) R/W_B hold time (to CS_B) Data hold time (to CS_B) CS_B pulse width Symbol tSADCS tSRWCS tSDACS tHADCSW tHRWCSW tHDACS tWCS Condition MIN. 10 10 10 10 10 10 4 x tCYTK TYP. MAX. Unit ns ns ns ns ns ns ns
Remark
tCYTK is the cycle of the TCLK clock.
tSADDS tHADCSW tWCS CS_B tSDACS MD0-MD7 DS_B tSRWCS R/W_B tHRWCSW Data tHDACS
MADD0-MADD6
Caution
If the device is reset via software by setting the CMR2 register, do not read or write all the registers for the duration of at least "20 x TCLK clock cycle (tCYTK)" from that write cycle. Otherwise, the registers may not be read or written correctly.
24
Data Sheet S11822EJ4V0DS00
PD98404
OAM interface
Parameter TCLK PHYARM2-0 delay time
Symbol tDARRL
Condition Load capacity = 50 pF
MIN.
TYP.
MAX. 25
Unit ns
TCLK tDARRL PHYARM2-0
Control signal interface
tDARRL
Parameter TFSS setup time (to TCL) TFSS hold time (to TCL) TCL TxFP delay time RCL RxFP delay time
Symbol tSTFTL tHTFTL tDTFTL tDRFRL
Condition
MIN. 20 5
TYP.
MAX.
Unit ns ns
Load capacity = 50 pF Load capacity = 50 pF
25 25
ns ns
TCL TFSS tSTFTL TxFP tHTFTL tDTFTL tDTFTL
RCL tDRFRL RxFP tDRFRL
Data Sheet S11822EJ4V0DS00
25
PD98404
UTOPIA interface (transmit side)
Parameter TCLK cycle time TCLK high level width TCLK low level width TCLK TCLAV delay time TCLK TCLAV output delay time TCLK TCLAV data float delay time TDI0-7 setup time (to TCLK) TDI0-7 hold time (to TCLK) TSOC setup time (to TCLK) TSOC hold time (to TCLK) TADD0-7 setup time (to TCLK) TADD0-7 hold time (to TCLK) TENBL_B setup time (to TCLK) TENBL_B hold time (to TCLK)
Symbol tCYTK tWTKH tWTKL tDCATK tVCATK tICATK tSDITK tHDITK tSSOTK tHSOTK tSADTK tHADTK tSENTK tHENTK
Condition
MIN. 25 0.4 x tCYTK 0.4 x tCYTK
TYP.
MAX. 50 0.6 x tCYTK 0.6 x tCYTK 19 19 25
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Load capacity = 50 pF Load capacity = 50 pF Load capacity = 50 pF
1 1 1 4 1 4 1 4 1 4 1
tCYTK tWTKH TCLK tSADTK TADD0-7 TCLAV tDCATK TENBL_B tSSOTK TSOC tSDITK TDI0-7 tHDITK tHSOTK tSENTK tHENTK tDCATK tICATK tVCATK tHADTK tWTKL
26
Data Sheet S11822EJ4V0DS00
PD98404
UTOPIA interface (receive side)
Parameter RCLK cycle time RCLK high level width RCLK low level width RCLK RCLAV delay time RCLK RCLAV output delay time RCLK RCLAV data float delay time RCLK RDO0-7 delay time RCLK RDO0-7 output delay time RCLK RDO0-7 data float delay time RCLK RSOC delay time RCLK RSOC output delay time RCLK RSOC data float delay time RADD0-7 setup time (to RCLK) RADD0-7 hold time (to RCLK) RENBL_B setup time (to RCLK) RENBL_B hold time (to RCLK)
Symbol tCYRK tWRKH tWRKL tDCARK tVCARK tICARK tDDORK tVDORK tIDORK tDSORK tVSORK tISORK tSADRK tHADRK tSENRK tHENRK
Condition
MIN. 25 0.4 x tCYRK 0.4 x tCYRK
TYP.
MAX.
Unit ns
0.6 x tCYRK 0.6 x tCYRK 19 19 25 19 19 25 19 19 25
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Load capacity = 50 pF Load capacity = 50 pF Load capacity = 50 pF Load capacity = 50 pF Load capacity = 50 pF Load capacity = 50 pF Load capacity = 50 pF Load capacity = 50 pF Load capacity = 50 pF
1 1 1 1 1 1 1 1 1 4 1 4 1
tCYTK tWTKH TCLK tSADTK TADD0-7 TCLAV tDCATK TENBL_B tSSOTK TSOC tSDITK TDI0-7 tHDITK tHSOTK tSENTK tHENTK tDCATK tICATK tVCATK tHADTK tWTKL
Data Sheet S11822EJ4V0DS00
27
PD98404
PMD parallel interface (receive side)
Parameter RPC cycle time RPC high level width RPC low level width RPD0 - RPD7 setup time (to RPC) RPD0 - RPD7 hold time (to RPC)
Symbol tCYRP tWRPH tWRPL tSPDRP tHPDRP
Condition
MIN. 50 0.4 x tCYRP 0.4 x tCYRP 10 5
TYP.
MAX.
Unit ns
0.6 x tCYRP 0.6 x tCYRP
ns ns ns ns
tCYRP tWRPH RPC tSPDRP RPD0-7 tHPDRP tWRPL
PMD parallel interface (transmit side)
Parameter TFC cycle time TFC high level width TFC low level width TFC TPC delay time TFC TPC delay time TPC TPD0-TPD7 delay time Symbol tCYTF tWTFH tWTFL tDPCTFH tDPCTFL tDPDTC Load capacity = 50 pF Load capacity = 50 pF Load capacity = 50 pF -5 Condition MIN. 50 0.4 x tCYTF 0.4 x tCYTF 0.6 x tCYTF 0.6 x tCYTF 25 25 +5 TYP. MAX. Unit ns ns ns ns ns ns
tCYTF tWTFH TFC tDPCTFH TPC tDPDTC TPD0-7 tDPCTFL tWTFL
28
Data Sheet S11822EJ4V0DS00
PD98404
PMD serial interface (transmit side)
Parameter REFCLK cycle time
Note
Symbol tCYRF tWRFH tWRFL tCYSF
Condition
MIN. -20ppm 0.4 x tCYRF 0.4 x tCYRF -0.005UI
TYP. 51.4403
MAX. +20ppm 0.6 x tCYRF 0.6 x tCYRF
Unit ns ns ns ns
REFCLK high level width REFCLK low level width TFKT(C) cycle time
6.43
+0.005UI
Caution
To get the TCL clock which is a jitter below 0.01UI, the basis signal which has at least equal to or more than 40 ppm precision must be inputted.
(i) When using a clock synthesizer
tCYRF tWRFH REFCLK tWRFL
(ii) When using an external serial clock
tCYSF TFKT (TFKC)
Data Sheet S11822EJ4V0DS00
29
PD98404
PMD serial interface (receive side)
Parameter RCIT(RCIC) cycle time RDIT(RCIC) setup time RDIT(RCIC) hold time
Symbol tCYSC tSDISC tHDISC
Condition
MIN. -0.005UI 3 1
TYP. 6.43
MAX. +0.005UI
Unit ns ns ns
tCYSC RCIT (RCIC) tSDISC RDIT (RDIC) tHDISC
30
Data Sheet S11822EJ4V0DS00
PD98404
3. PACKAGE DRAWINGS
144 PIN PLASTIC QFP (FINE PITCH) (20x20)
A B
108 109 73 72
detail of lead end S C D Q R
144 1
37 36
F G P H I
M
J K M
N
NOTE
S
L
S
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 22.00.3 20.00.2 20.00.2 22.00.3 1.25 1.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.17 +0.03 -0.07 0.10 2.7 0.1250.075 3 +7 -3 3.0 MAX.
Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
S144GJ-50-JEU, KEU-1
Data Sheet S11822EJ4V0DS00
31
PD98404
4. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document "Semiconductor Device Mounting Technology Manual" (C10535E). For soldering methods and conditions other than those recommended below, contact our sales personnel. Surface Mount Type Soldering Conditions * PD98404GJ-KEU: 144-pin plastic QFP (fine pitch) (20 x 20 mm)
Recommended soldering code IR35-203-2
Soldering method Infrared reflow
Soldering conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: two times or less Note Exposure limit: 3 days (after that, prebake at 125C for 20 hours) Pin temperature: 300C max., Duration: 3 seconds max. (per device side)
Partial heating
-
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period.
32
Data Sheet S11822EJ4V0DS00
PD98404
[MEMO]
Data Sheet S11822EJ4V0DS00
33
PD98404
[MEMO]
34
Data Sheet S11822EJ4V0DS00
PD98404
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S11822EJ4V0DS00
35
PD98404
NEASCOT-P30, NEASCOT-S15, and NEASCOT-X15 are trademarks of NEC Corporation.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98. 8

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